Vertical-cavity surface-emitting laser (VCSEL which is referred to as simply surface-emitting laser device or VCSEL device hereinafter) is a semiconductor laser device which emits laser light in the direction perpendicular to the substrate surface thereof. The surface-emitting laser device is such that a large number of VCSEL devices can be arranged in a two-dimensional array on a common substrate, and now attracts an attention as a light source in the field of communication as well as a specific device for a variety of applications.
The VCSEL device has a resonator structure, wherein a pair of semiconductor distributed-Brag-reflector mirrors (DBR mirrors) are formed on a semiconductor substrate such as GaAs or InP, and an active layer configuring an emission region is provided between the pair of DBR mirrors. For example, a GaAs-group VCSEL device can be formed on a GaAs substrate, and AlGaAs-based DBR mirrors (such as including AlAs/AlGaAs layer pairs) having an excellent heat conductivity and a higher reflectance can be used. Thus, the GaAs-group VCSEL device is expected as a promising laser device emitting a light having a wavelength range between 0.8 μm and 1.0 μm. In addition, a VCSEL device including an active layer configured by GaInNAs-based materials is expected as a promising laser device which emits laser of a longer wavelength range between 1.2 μm and 1.6 μm.
As a VCSEL device, an oxide-confinement-type surface-emitting semiconductor laser device is proposed which has a structure wherein an Al-oxidized layer confines the current injection area for improving the current efficiency and reducing the threshold current thereof.
With reference to FIG. 10, the configuration of a conventional surface-emitting semiconductor laser device used in a 850-nm-wavelength range and having an oxide-layer-confinement structure will be described hereinafter. FIG. 10 is a perspective sectional view depicting the configuration of the conventional 850-nm-range surface-emitting semiconductor laser device having the oxide-layer-confinement structure. The surface-emitting semiconductor laser device 100 has, on a p-type GaAs (p-GaAs) substrate 62, a layer structure including a buffer layer 63, a bottom DBR mirror 64 including 35 pairs of p-Al0.9GaAs/p-Al0.2GaAs layers each having a layer thickness corresponding to λ/4n (λ and n are emission wavelength and refractive index, respectively), a lower cladding layer 66, a quantum-well active layer 68, an upper cladding layer 70, and a top DBR mirror 72 having 25 pairs of n-Al0.9GaAs/n-Al0.2GaAs layers each having a layer thickness corresponding to λ/4n.
In the bottom DBR mirror 64, one of the Al0.9GaAs layers disposed in the vicinity of the quantum-well active layer 68 is replaced by an AlAs layer 74, and the Al in an area of the AlAs layer 74 other than the central current-injection area thereof is selectively oxidized to configure an Al-oxidized layer 75 as the current-confinement layer. A part of the layer structure disposed between the top portion thereof and a portion of the bottom DBR mirror is configured as a mesa-post 80, on which a ring electrode 82 is formed. The conventional VCSEL device 100 having the above structure is manufactured by a process as described below.
First, semiconductor layers configuring the layer structure are deposited using an epitaxial-growth technique. Subsequently, a portion of the layer structure disposed between the top DBR mirror 72 and a portion of the bottom DBR mirror 64 is subjected to an etching treatment using a photolithographic and etching process, to configure a cylindrical mesa-post 80 having a diameter of 30 μm, for example. In the step of forming the mesa-post 80, a configuration may be employed wherein a semiconductor layer portion other than the mesa-post 80 is removed by etching in its entirety, or an annular groove is formed by the etching to configure the mesa-post inside the annular groove and a peripheral area surrounding the annular groove. The example shown in the figure is such that the portion of the semiconductor layers other than the mesa-post 80 is removed by etching in its entirety.
An oxidation process is conducted wherein the layer structure configured as the mesa-post 80 is maintained in a steam atmosphere at a temperature of about 400 degrees C., to thereby selectively oxidize the Al in the AlAs layer 74 from outside of the mesa-post 80, whereby a current confinement layer including the Al-oxidized layer 75 is formed within the AlAs layer 74.
Subsequently, a SiNx passivation layer 76 is formed over the entire area of the wafer including the top surface and side surface of the mesa-post 80 and a portion of the p-type bottom DBR mirror 64 near the mesa-post 80. Thereafter, a polyimide film 78 is formed on the entire area of the wafer by coating, followed by curing the polyimide film 78 in a three-step heat treatment wherein temperatures of 200 degrees C., 300 degrees C. and 400 degrees C. are maintained for 40 minutes, 60 minutes and 60 minutes, respectively. Subsequently, a photolithographic process is conducted to remove a portion of the polyimide film 78 on the top surface of the mesa-post 80, thereby exposing the SiNx passivation layer 76. The polyimide film 78, which is formed by coating to have a substantially uniform thickness, is subjected to the influence by the contraction etc. of the polyimide due to the post-coating heat treatment, thereby assuming a shape wherein the polyimide film is highest at the mesa-post area and gradually reduces the height in the peripheral portion.
Subsequently, an RIE system is used to etch a portion of the SiNx passivation layer 76 exposed on the mesa-post 80 by using CF4 gas as an etching gas, thereby forming a window for forming therethrough an n-side electrode. Thereafter, a metallic film is formed by evaporation to form a ring-shaped n-side electrode 82. After forming the n-side electrode 82, the bottom surface of the p-GaAs substrate 62 is polished to adjust the substrate thickness to 200 μm, followed by forming a metallic film on the bottom surface of the substrate by evaporation to form a p-side electrode 86. Subsequently, an electrode anneal is conducted at an anneal temperature of 400 degrees C. for 3 minutes. After those steps as recited above, the wafer process is finished. Subsequently, the wafer is subjected to dicing using a dicing machine to formulate devices, whereby surface-emitting semiconductor laser devices 10A such as shown in FIG. 10 can be obtained. Those devices manufactured in the manner as described above are subjected to measurement tests such as for electric characteristics thereof, and mounted on an optical module etc. after the assembly steps. Conventional VCSEL devices are described in JP-2003-69150A1 and JP-2000-68604A1, for example.
As described above, the VCSEL device is embedded within the polyimide film in its entirety, and then subjected to the polishing process for the bottom surface of the substrate, testing process and assembly process, after the portion of the polyimide film on the top surface of the mesa-post is removed. In those processes, handling of the VCSEL device causes a contact with respect to a variety of testing equipments and jigs, or applies a mechanical pressure etc. thereon.
In the testing process, as shown in FIG. 11(a), a measurement probe 40 is shifted on the surface of the wafer on which the mesa-post 80 is formed, in order to contact the measurement probe 40 with the ring electrode 82 of the VCSEL device. Thus, the measurement probe 40 is likely to contact the mesa-post 80. In addition, as shown in FIG. 11(b), if the measurement probe 40 contacts the pad electrodes 42 which is formed on the polyimide film 78 in the peripheral area outside the mesa-post 80 and electrically connected to the ring electrode 82, a stress caused by the measurement probe 40 is applied to the mesa-post 80 through the polyimide film 78.
During the polishing process for the bottom surface of the substrate, as shown in FIG. 11 (c), a portion of the top surface of the mesa-post 80 of the VCSEL device is attached onto a polishing jig 44, and the polishing is performed in this state. In this case, the attachment of the polishing jig 44 onto the portion configured by the bay window of the mesa-post 80 for emitting therethrough the laser beam is likely to cause a defect on the mesa-post 80. In the assembly process to the optical module, the VCSEL device is likely to contact an optical fiber on the top surface of the mesa-post upon coupling thereof to the optical fiber. Further, before and after the testing process or assembly process, the VCSEL device is likely to be damaged also by a jig such as a pincette upon holding the same by the jig.
As described above, there is a problem in the process for handling the VCSEL device that the mesa-post 80 of the VCSEL device is likely to be damaged on the surface of the mesa-post 80 by a contact with respect to a variety of testing equipments or jigs due to a protruding structure thereof protruding from the peripheral area, or that the VCSEL device is damaged on the mesa-post 80 having therein the resonator structure due to a stress applied thereto.
A method of performing a wafer level burn-in test for surface-emitting laser devices is disclosed in Japanese Patent Application Publication No. 2005-209928. In this prior art, an example which performs Burn-in for surface-emitting laser devices in the situation mounted on can package and an example which performs Burn-in for surface-emitting laser devices in a chip formed in a bar.
Meanwhile, in a fabricating process for the above surface-emitting laser devices, it is required to perform a wafer level burn-in test for a plurality of surface-emitting laser devices formed on a wafer, from the viewpoints of shortening the fabricating process and improving the product yield. Here, a wafer level burn-in test is a technology which screens at a time effectively reliability failures of surface-emitting laser devices formed on wafer.